英语单词

NMOS的中文翻译

NMOS

英[] 美[]
  • abbr. 通道金属氧化半导体(N-channel metal oxide semiconductor FET);国家制图机构(national mapping organisations);电晶体

双语例句


1. Integrated circuit. NMOS, asynchronous communications interface adapter.
集成电路。NMOS管,异步通信接口适配器。

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2. Two power amplifier output stage using PMOS and NMOS transistors by the special design.
两个功率放大器的输出级均采用PMOS和NMOS晶体管特殊设计而成。

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3. The substrate-triggered technique has an obvious improve on ESD level of the large-dimension NMOS devices.
衬底触发技术可以大幅度提高大尺寸NMOS器件的ESD级别。

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4. The high precision resistor is composed of three NMOS FETs with controllable gate voltage and aspect ratios.
通过控制各MOS 管的栅电压和宽长比可得到线形度较好的高精度电阻器。

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5. A regular NMOS-only M-2M ladder and a current-to-voltage conversion circuit proposed in this paper are adopted in this design.
设计中,采用了一种规则的全NMOS管构成的M-2M梯形电路,以及本文提出的电流-电压转换电路。

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6. A depleted NMOS transistor, which was used as current source, and a negative feedback loop constitute a stable voltage reference.
该电路采用耗尽型NMOS管作电流源器件,结合负反馈,实现了稳定的电压基准。

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7. Through inductor optimization, the VCO has a low phase noise and a wide tuning range with switched capacitor array and NMOS varactor.
通过优化集成电感的设计,同时采用NMOS管和开关电容阵列作为可变电容,使该设计具有较低的相位噪声和较宽的调谐范围。

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8. Based on the SWB environment, the design for manufacturing and optimization of the nano-level NMOS integrated chips were implemented.
基于SWB环境实现了nm级NMOS集成化管芯的可制造性设计及优化。

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9. The gate electrodes (16) of the NMOS transistors (a) are formed in a layer of n-type doped polycrystalline silicon (14) without germanium.
NMOS晶体管(A)的门电极(16)在n -型掺杂的不含锗的多晶硅层(14)上形成。

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10. Total-dose irradiation effect of partially-depleted NMOS transistors with gate-all-around and H-gate structures fabricated on modified SIMOX was studied.
研究了在改性注氧隔离(SIMOX)材料上制备的具有环栅和H型栅结构的部分耗尽NMOS晶体管在三种不同偏置状态的总剂量辐照效应。

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11. On the basis of the multiple-valued switch-level algebra, this paper proposes a logic design automation algorithm for NMOS and CMOS combinational circuits.
本文在多值开关级代数理论的基础上,提出了适合于NMOS及CMOS组合电路的逻辑设计自动化算法。

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12. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate.
于本发明第一实施例中包括一nmos晶体管、一pmos与一双极晶体管形成于基底的不同区域。

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13. Based on simulation, the characteristics and mechanisms of failure on a deep sub-micron grounded-gate NMOS (GGNMOS) are studied under TLP (transmission line pulse) stress.
对TLP(传输线脉冲)应力下深亚微米ggnmos器件的特性和失效机理进行了仿真研究。

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14. At the same time, to prevent the generation of latch-up, guard rings are added around the large dimension digital output inverter PMOS and NMOS transistors of the circuits.
同时,为了防止闩锁效应的产生,在电路的大尺寸数字输出反相器的PMOS管和NMOS管的周围增加了保护环。

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15. The estimated values agree quite well with tests and the results indicate that VVMOS power FET is compatible with NMOS integrated circuits even by conventional processing technology.
结果指出,即使用常规工艺制造技术把VVMOS功率晶体管相容集成到NMOS电路中去亦是可能的。

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16. For example, the hole mobility in PMOS and the electron mobility in NMOS can be significantly enhanced by introducing appropriate compressive and tensile channel stresses, respectively.
例如,通过在沟道中引入适当的压应力和张应力能分别提高PMOS的空穴迁移率和NMOS的电子迁移率。

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17. Wafer-level, laser-trimmed, thin-film resistors and temperature-compensated NMOS switches assure operation over the full operating temperature range with exceptional lin- ear and gain stability.
晶圆级,激光微调,薄膜电阻和温度,真实姿态补偿NMOS管开关保证在整个工作温度和特殊林耳和经营范围的增益稳定性。

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18. The A1210-A1214 Hall-effect latches include the following on a single silicon chip: voltage regulator, Hall-voltage generator, small-signal amplifier, Schmitt trigger, and NMOS output transistor.
在A1210 - A 1214霍尔效应锁存包括一个单一的硅芯片上以下内容:稳压器,霍尔电压发生器,小信号放大器,施密特触发器和NMOS输出晶体管。

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19. The A1210-A1214 Hall-effect latches include the following on a single silicon chip: voltage regulator, Hall-voltage generator, small-signal amplifier, Schmitt trigger, and NMOS output transistor.
在A1210 - A 1214霍尔效应锁存包括一个单一的硅芯片上以下内容:稳压器,霍尔电压发生器,小信号放大器,施密特触发器和NMOS输出晶体管。

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