VHDL
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- abbr. 硬件描述语言（Hardware Description Language）；甚高速集成电路硬件描述语言（Very High Speed Integrated Circuits Hardware Description Language）
双语例句
- 1. And the programmable language is used VHDL.
- 在设计中所用编程语言是VHDL。
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- 2. The 28 bit plus-minus counter was realized in VHDL.
- 用VHDL语言设计实现了28位加减计数器。
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- 3. The program is compiled with VHDL(hardware description language).
- 试验程序由VHDL硬件描述语言编写。
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- 4. VHDL is very suitable to the design of programmable logic devices.
- VHDL非常适用于可编程逻辑器件的应用设计。
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- 5. Variable presents a specific feature of VHDL sequential statements.
- 变量是VHDL 语言中顺序语句的一个特征。
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- 6. The model of RAID channel adapter de-scribed by VHDL is put forward.
- 提出了用硬件描述语言VHDL描述RAID通道适配器模型。
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- 7. VHDL hardware description language based, a very good book, time to take a look!
- VHDL硬件描述语言基础，非常好的一本书，有时间不妨看看！
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- 8. The VHDL export for IM (induction motor module) now takes iron loss into account.
- IM VHDL出口(感应电机模块)现在需要铁缺乏考虑。
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- 9. In this paper, a kind of chip of video complex black signal is described with VHDL.
- 采用VHDL硬件描述语言设计一种再生视频复合消隐信号的专用芯片。
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- 10. The course requires extensive use of VHDL for describing and implementing digital logic designs.
- 这课程需要使用VHDL去描述和执行数字逻辑设计。
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- 11. The methods to solve several problems of designing VHDL synthesis system are given in this paper.
- 讨论了在研究和设计VHDL综合系统时遇到的若干问题的解决方案。
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- 12. Through design examples, this paper introduces the method of digital systems design based on VHDL.
- 通过设计实例，介绍了利用VHDL语言进行数字系统设计的方法。
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- 13. The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.
- 用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。
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- 14. Lastly, the hardware circuit, VHDL program design and debugging methods based on FPGA are discussed.
- 最后对基于现场可编程门阵列(FPGA)的硬件电路、VHDL语言程序设计及调试方法进行了讨论。
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- 15. This is written in VHDL 32 dividers procedures can be run directly see the results, welcomed the use.
- 这是用VHDL语言写的32位分频器的程序，可直接运行，看结果，欢迎使用。
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- 16. Therefore, it is essential to study how to predigest actual circuit and achieve optimized design in VHDL.
- 因此，有必要深入讨论在VHDL设计设计、应用中如何简化实际电路，达到优化设计的要求。
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- 17. This paper deals design method of digital system of top-down, VHDL and applications of in technology ASIC.
- 本文论述了数字系统自顶向下的设计方法、VHDL及其在ASIC技术中的应用。
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- 18. The paper proposes a mew method for testing combinational digital circuit which is based on the VHDL language.
- 本文提出了一种新的基于VHDL语言的组合数字电路测试码自动生成方法。
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- 19. VHDL is considered as a core of digital system design and a key technique of implement digital systems design.
- 硬件描述语言(VHDL)是数字系统高层设计的核心，是实现数字系统设计新方法的关键技术之一。
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- 20. This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system.
- 介绍了VHDL逻辑级模拟系统中模拟模块的设计和实现。
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- 21. VHDL language is the important tool of electronic design, and data object is one of essential language factors.
- VHDL语言是现代电子设计的重要工具，数据对象是其中的重要语言要素。
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- 22. This article studied how to design a counter based on VHDL which will be applied in drip-irrigation controller.
- 本文针对VHDL在滴灌控制器的定时器芯片的设计展开研究。
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- 23. The serial communication interface chip design was realized by application of schematic diagram and VHDL language.
- 采用自顶向下的设计方法，用原理图和VHDL语言这两种输入对串行通信接口芯片进行设计。
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- 24. The design of source files by VHDL, compilation and synthesis, and implementation methods with HDPLD are discussed.
- 着重讨论了用VHDL设计源文件，通过综合编译，用HDPLD实现的方法。
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- 25. VHDL can provide high level language structure, describe large scale circuit conveniently and complete design rapidly.
- VHDL能提供高级语言结构，方便地描述大型电路，快速地完成设计。
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- 26. A general method of intelligent controller design and closed-loop test based on VHDL and FPGA implementation is proposed.
- 提出了一种基于VHDL描述、FPGA实现的智能控制器设计和闭环测试的一般性方法。
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- 27. With the analysis of the experimental outcome, this article introduces the superiority of VHDL in the digital circuit design.
- 通过对设计结果的分析，阐述了VHDL在数字电路设计中的优越性。
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- 28. Summarized the concurrent statements and sequential statements of VHDL language, and described their types and the characteristic.
- 简单概述了VHDL语言的并行语句和顺序语句，描述了其种类和特点。
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- 29. The logic synthesis of VHDL language is a method that the description of higher abstract hierarchy is shifted to lower one automatically.
- VHDL语言的逻辑综合就是将较高抽象层次的描述自动转换到较低抽象层次描述的一种方法。
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- 30. The logic synthesis of VHDL language is a method that the description of higher abstract hierarchy is shifted to lower one automatically.
- VHDL语言的逻辑综合就是将较高抽象层次的描述自动转换到较低抽象层次描述的一种方法。
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